ps - For anyone with this board or similar from SuperMicro. They recommend me to leave the memory exactly how i had it. A1, A2, B1, B2. basically on one side of the CPU. This way it gives me the best performance and it operates in Memory Interleaving. Any other way, it won't do Memory Interleaving.
In that case, if you don't mind, it'd be nice to know if any weird problems arise when slots A1, B1, C1 and D1 are populated, with the rest empty, and vice-versa.
Was anyone ever able to do any testing with 4 sticks of ram in the X10SRH-CLN4F to see which slots actually need to be populated to take advantage of quad-channel ram?
To recap, previous manuals for boards in the X10 generation stated to populate DIMMS as follows:
DIMM-A1, DIMM-B1, DIMM-C1, DIMM-D1; DIMM-A2, DIMM-B2, DIMM-C2, DIMM-D2.
The quick-guide for the X10SRH-CLN4F and a phone tech with SM stated to populate DIMMS as follows (for "Balanced" performance, whatever that means):
DIMM-A1, DIMM-A2, DIMM-B1, DIMM-B2; DIMM-C1, DIMM-C2, DIMM-D1, DIMM-D2.
This board has FOUR channels (A, B, C, D) and TWO Banks (1 & 2). I have a sneaking suspicion that to get both quad-channel performance (A,B,C,D) AND memory interleave (1 & 2), one stick in each DIMM Bank (e.g. Bank 1), and two sticks in each DIMM channel (E.g. Ch. A) are required. E.g. each of the 8 memory slots require a DIMM for optimal performance.
Can anyone confirm? I would think this could be confirmed with MemTest since it indicates various speeds and memory bandwidth.
Quick-Reference Charts from two different SuperServers that contain the X10SRH-CLN4F board:
http://www.supermicro.com/QuickRefs/superserver/2U/QRG-1607.pdf
http://www.supermicro.com/QuickRefs/superserver/4U/QRG-1609.pdf