Please help me understanding pcie lanes. (Asrock X570m PRO - Ryzen 5 PRO 4650G)!!

Oedzesg

Dabbler
Joined
Oct 24, 2020
Messages
19
Hallo all,

Unfortunately, AMD does not provide all the information about the PCIE Lanes of the Ryzen 5 PRO 4650G on their site.

I use this CPU in combination with an ASROCK X570M PRO.
If I understand correctly, pcie slot_1 and slot_3 run on X16 when used alone.

if both slots are in use, slot_3 will still have x4 available and slot_1 will continue to run at x16.
These PCIE x16 slots are directly connected to the CPU.

My mobo has 2 m.2 connections. 1 of these is also directly connected to the CPU via 4 lanes.

Maybe a stupid question but I can't find anywhere in the documentation which of the 2?

In addition, the CPU communicates with the chipset through 4 lanes.
The 2nd m.2 slot is connected via this chipset and also the 8 sata ports and the last PCIEx1 port.

If I have also understood this correctly, not all 8 sata connections are available anymore when I use the 2nd m.2 slot.
Again I can't find anywhere which ports are blocked.

As indicated, not all information about the number of PCIE lanes is listed on AMD's site, but I read somewhere that 20 lanes are available.

In my current setup:

* Silverstone CS381 case.
* All 8 drives connected to the backplane via LSI HABA card.
* m.2 120 gbit as boot drive.

Since I only use this setup as a nas, this works fine.

What I would like:

* adding a 2 port 10gbe network card in the 2nd X16 slot.
So it runs at 3.0x4 which is sufficient as far as I've read

* Add 2nd nvme for temporary files (e.g. the
extracting downloaded files via NZBGet).

* Add 2 internal SSD through the sata ports for using
Docker.

My simple mind then tells me that this won't work because I don't have enough lanes available from my CPU.

PCIE slot_1 = 16 lanes
PCIE slot_2 = 4 lanes
NVME_1 = 4 lanes
Motherboard connection to the chipset = 4 lanes

This is a total of 28 lanes which I do not have available.

Am I completely missing the point and are you laughing at me? Or is it correct as I think?

I hope there is someone who can give me a clear explanation.

Thank you very much!
 

Etorix

Wizard
Joined
Dec 30, 2020
Messages
2,134
Unfortunately, AMD does not provide all the information about the PCIE Lanes of the Ryzen 5 PRO 4650G on their site.
Or the combination of a long-lasting socket, which has seen many different generations of CPUs with different capabilities, the use of code names to designate these generations rather than a straightforward numbering scheme, AND a consumer-grade motherboard whose documentation lacks a block diagram, makes it unnecessarily complex.

Let's try. Ryzen 5 PRO 4650G is "Renoir".
I use this CPU in combination with an ASROCK X570M PRO.
Specifications
Renoir can always use both PCIe slots 1 and 3 at x16 and x4.

My mobo has 2 m.2 connections. 1 of these is also directly connected to the CPU via 4 lanes.

Maybe a stupid question but I can't find anywhere in the documentation which of the 2?
Ask the manufacturer's support for a block diagram.
In addition, the CPU communicates with the chipset through 4 lanes.
The 2nd m.2 slot is connected via this chipset and also the 8 sata ports and the last PCIEx1 port.
So you actually know?
If I have also understood this correctly, not all 8 sata connections are available anymore when I use the 2nd m.2 slot.
Not sure where you have seen that. Typically a PCH SATA lane may be shared between a SATA port and a M.2 slot but NVMe is not affected: If the M.2 slot holds a NVMe drive, all SATA ports are usable.

As indicated, not all information about the number of PCIE lanes is listed on AMD's site, but I read somewhere that 20 lanes are available.
x16 + x4 for the two PCIe slots (where x16/x0 or x8/x8 plus x4 for a M.2 slot could have been a better choice)
downstream lanes for the PCH are typically not counted as "available"

Both M.2 slots should then hang from the PCH.
 

Oedzesg

Dabbler
Joined
Oct 24, 2020
Messages
19
1671730271808.png
 

Oedzesg

Dabbler
Joined
Oct 24, 2020
Messages
19
Thnx!

so it looks like lots of devices share the 4 lanes between de cpu and the chipset.
 
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